This invention relates to Phase-locked loops (PLL""s), and more particularly to PLL""s with reduced noise.
Digital systems often rely on accurate clocks to synchronize the timing of operations and data transfers. A crystal oscillator can be used to generate a clock at a base frequency, which is then divided or multiplied to create one ore more clocks with desired frequencies. External clock can be received and likewise divided or multiplied to produce internal clocks.
Clocks are typically generated from oscillator outputs using phase-locked loops (PLL""s). PLLs are one of the most widely use building blocks in digital systems today. FIG. 1 illustrates a typical PLL. Phase detector 10 receives a reference-clock input from an external oscillator or clock source. The phase and frequency of the reference clock is compared to the phase and frequency of a feedback clock generated by voltage-controlled,oscillator (VCO) 14. The feedback clock can be the output clock generated by the PLL, or a divided-down derivative of the output clock from VCO 14 such as produced by feedback counter 16.
Phase detector 10 outputs up and down signals UP, DN when the phase or frequency of one input does not match the phase or frequency of the other input. These up and down signals cause charge pump 12 to add or remove charge from filter capacitor 20, which integrates the charge. As charge is added or removed through resistor 21 from filter capacitor 20, the voltage input to VCO 14 is increased or decreased. VCO 14 responds by increasing or decreasing the frequency of the output clock. The feedback clock to phase detector 10 is likewise changed by VCO 14.
As charge pump 12 adds or removes charge from filter capacitor 20, altering control voltage VCTL input to VCO 14, the phase and frequency of the feedback clock are adjusted until the reference clock is matched. Then phase detector 10 stops generating up and down signals to charge pump 12, until charge leaks off filter capacitor 20 or the reference clock changes.
Pulses of short duration are often used for up and down signals UP, DN. For example, phase detector 10 can be a pair of simple flip-flops. One flip-flop outputs the UP pulse when clocked by the reference-clock input. The UP pulse ends when cleared by the feedback-clock input. The other flip-flop generates the DN pulse when clocked by the feedback-clock input. The DN pulse ends when cleared by the reference-clock input. As the phases match more closely, the duration of the pulses shorten.
Often both up and down signals are pulsed simultaneously when no phase adjustment is needed. Charge pump 12 should supply either no charge or equal up and down charges to filter capacitor 20 so that a net zero charge is supplied when the duration of simultaneous UP and DN pulses are identical.
Since clocks are intended to be stable, most of the time charge pump 12 is outputting a net zero charge to filter capacitor 20. If the UP and DN sections of charge pump 12 are not matched exactly, some net charge may be applied to filter capacitor 20. This net charge results in a phase error, since VCO 14 responds by slightly changing the phase and frequency of the feedback clock so that it no longer exactly matches the reference clock.
FIG. 2 is a timing diagram of UP and DOWN inputs to a charge pump and the resulting control voltage to the VCO. When a leading phase difference is detected by the phase detector, an UP pulse is generated. The charge pump responds to the UP pulse by pumping positive charge to the filter capacitor, increasing the control voltage VCTL to the VCO. The amount of charge pumped to the filter capacitor depends on the duration of the UP pulse. Once the UP pulse ends, the control voltage remains stable.
When a lagging phase difference is detected by the phase detector, a DN pulse is generated. The charge pump responds to the DN pulse by sinking charge from the filter capacitor, decreasing the control voltage VCTL to the VCO. The amount of charge pumped from the filter capacitor depends on the duration of the DN pulse. Once the DN pulse ends, the control voltage remains stable.
Finally, as FIG. 2 shows, the phases are matched and the phase detector outputs both UP and DN pulses simultaneously. The control voltage should not change, but the charge pump is not perfect and causes some noise on the control voltage as transistors in the charge pump are switched on and off by the UP and DN pulses. Should the UP and DN pump transistors not match, a net charge can be added to the control voltage as shown. This net charge is an error caused by the charge pump that reduces the accuracy of the PLL.
Noise is a key metric of a PLL. Noise can be generated by the VCO and other components such as the charge pump. Noise can also be input on the reference clock and propagated to the output. Noise can manifest itself as clock jitter or in other ways.
The noise sources in a PLL system can be separated into noise sources before the loop filter and noise sources after the loop filter. For noise sources after the loop filter, the major contributor is the VCO. The VCO noise can be separated into inner band noise and outer band noise. Inner band noise has a frequency components less than the loop bandwidth, while outer band noise has frequency components greater than the loop bandwidth.
Because noise from the VCO is inserted into the PLL after the loop filter, the outer band noise appears on the output of the PLL. Inner band noise can be compensated by the PLL. For noise sources before the loop filter, the behavior is opposite of VCO noise. The pre-filter inner band noise passes through the loop filter and appears on the output, while the outer band noise is filtered out by the loop filter.
What is desired is a PLL with reduced noise. An improved PLL that removes noise created by the VCO is desirable. Although inner-band noise from the VCO can be suppressed by the loop filter, outer band noise is not suppressed by the loop filter. A PLL with circuitry to reduce outer-band noise from the VCO is desired.